Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on or in a surface of a semiconductor wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as scratches, roughness, or embedded particles of dirt or dust. The polishing process can be accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
In these polishing processes, it is often important to determine an endpoint of the polishing process. Overpolishing (removing too much) of a conductive layer results in increased circuit resistance and potential scrapping of the semiconductor wafer. Since many processing steps have occurred prior to the polishing process, scrapping a semiconductor wafer during fabrication may undesirably result in significant financial loss. Underpolishing (removing too little) of a conductive layer on the other hand leads to failure in isolating circuits and results in electrical shorts. Presence of such electrical shorts leads to rework (redoing the CMP process) thereby disadvantageously increasing costs (e.g. production costs) associated with the semiconductor wafer. Thus, a precise endpoint detection technique is needed.
A typical method employed for determining the endpoint in polishing systems is to measure the amount of time needed to planarize a first wafer, and thereafter polishing the remaining wafers for a similar amount of time. In practice this method is extremely time consuming since machine operators must inspect each wafer after polishing. In particular, it is extremely difficult to precisely control the removal rate of material since the removal rate may vary during the polishing of an individual wafer. Moreover, the removal rate may be diminished in the process of polishing a number of wafers in sequence.
Another approach employed for determining the endpoint in polishing systems is to utilize an optical end point method. Generally, optical end point methods include the use of an optical unit, a control system (i.e. a computer) to control the polishing process, and a layer of material positioned on the semiconductor wafer which has a predetermined reflectivity characteristic. With respect to the reflectivity characteristics of a material, some materials absorb light as opposed to reflecting it, these types of materials have a relatively low reflectivity. On the other hand, some materials reflect light as opposed to absorbing it, these types of materials possess a relatively high reflectivity. Therefore, a material having a predetermined reflectivity characteristic, such as high reflectivity, can be selected and layered onto a semiconductor wafer at a position which represents the desired end point of the polishing process. In addition, the material having the predetermined reflectivity is positioned underneath at least one other layer of material which has a different reflectivity characteristic. As the polishing procedure proceeds, the superimposed layer is gradually removed so as to expose the material having the predetermined reflectivity to a laser beam generated by the optical unit. Once the material having the predetermined reflectivity is exposed, it reflects the laser beam such that the optical detector detects the characteristic reflection and terminates the polishing process in response thereto.
However, a problem with optical end point methods is that they do not work well with semiconductor wafers having patterns or trenches defined therein. For example, optical end point methods do not work well with semiconductor wafers fabricated utilizing a shallow trench isolation (STI) process. Specifically, the previously discussed characteristic reflection which terminates the polishing process is difficult to detect on a semiconductor wafer fabricated utilizing an STI process. In particular, the characteristic reflection tends to be relatively weak and thus difficult to detect. Therefore, it is more likely that the polishing process will not be terminated at the appropriate time which results in damage to the semiconductor wafer.
Thus, a continuing need exists for a method which accurately and efficiently detects when a polishing system polishes a semiconductor device down to a desired polishing endpoint layer. Moreover, a continuing need exists for a method which accurately and efficiently detects when a polishing system polishes a semiconductor device having patterns or trenches defined therein down to a desired polishing endpoint layer.